Flash memory device having recessed floating gate and method for fabricating the same

ABSTRACT

A flash memory device and a method for fabricating the same are provided. The flash memory device includes: an active region having a plurality of surface regions and a plurality of recess regions formed lower than the surface regions; a tunnel oxide layer formed over the recess regions; a plurality of recessed floating gates formed over the tunnel oxide layer to be buried into the recess regions; a plurality of dielectric layers over the recessed floating gates; and a plurality of control gates over the dielectric layers.

FIELD OF THE INVENTION

The present invention relates to a method for fabricating asemiconductor device; and more particularly, to a flash memory deviceand a method for fabricating the same.

DESCRIPTION OF RELATED ARTS

Recently, a high integration technology of a memory device has beenactively studied to develop a memory device with a high capacitancecapable of storing, programming and erasing a large amount of data.

If a design rule is decreased for a high integration, a gate length isdecreased. Accordingly, a doping concentration is increased whileperforming a threshold voltage adjustment ion-implantation capable ofcontrolling a threshold voltage.

Typically, if the doping concentration implanted within a substrate isincreased, an electric field between source/drains and a junctionleakage current are increased, and a short channel effect such as adrain induced barrier lowering (DIBL) phenomenon is generated. A basicmethod to prevent the short channel effect from being generated is todecrease a doping concentration of a substrate or increase an effectivegate length.

FIG. 1 is a top view illustrating a typical flash memory device. FIGS.2A and 2B are cross-sectional views illustrating FIG. 1 cut along a lineI-I′ and FIG. 1 cut along a line II-II′ respectively.

As shown in FIG. 1, a plurality of device isolation layers 12 are placedin a substrate 11 spaced apart a predetermined distance in the samedirection. A plurality of control gates CG 16 covering a plurality offloating gates FG 14 formed in an active region 11A between the deviceisolation layers 12 are formed in a direction perpendicular to thedevice isolation layers 12. Herein, the control gates CG 15 arepractically placed in the direction perpendicular to the deviceisolation layer 12, and the floating gates FG 14 are formed only in theintersection point between the control gates CG 16 and the active region11A.

Referring to FIGS. 2A and 2B to examine the floating gates FG 14, aplurality of device isolation layers 12 with a trench structure areformed with a predetermined distance in a substrate 11. At this time, anactive region 11A is formed between the device isolation layers 12, andthe device isolation layers 12 have a higher height than the activeregion 11A.

A plurality of stack structures formed by stacking a tunnel oxide layer13 and the floating gates 14 are formed over the active region 11A. Aplurality of oxide/nitride oxide (ONO) layers 15 are formed over anentire surface including the floating gates FG 14, and a plurality ofcontrol gates CG 16 are formed over the ONO layers 15. At this time, thecontrol gates CG 16 cover the floating gates 14 and are placed in a lineshape covering the device isolation layers 12.

As for the conventional flash memory device, a gate line formed with afloating gate and a control gate is formed over a flat active region.Thus, the conventional flash memory device becomes a planar typestructure.

However, in the conventional planar gate structure, an effective gatelength is decided by a line width of the floating gate and thus, theeffective gate length is very short. Accordingly, a short channel effect(SCE) is increased, and thus, it is difficult to make a highlyintegrated NAND flash memory device.

SUMMARY OF THE INVENTION

It is, therefore, an object of the present invention to provide a flashmemory device capable of preventing a doping concentration of asubstrate from being increased as a device has been integrated andsecuring an electrical property of the device by increasing an effectivegate length, and a method for fabricating the same.

In accordance with one aspect of the present invention, there isprovided a flash memory device including: an active region having aplurality of surface regions and a plurality of recess regions formedlower than the surface regions; a tunnel oxide layer formed over therecess regions; a plurality of recessed floating gates formed over thetunnel oxide layer to be buried into the recess regions; a plurality ofdielectric layers over the recessed floating gates; and a plurality ofcontrol gates over the dielectric layers.

In accordance with another aspect of the present invention, there isprovided a method for fabricating a flash memory device including:forming a plurality of device isolation layers with a trench structureand a height greater than that of a surface of an active region in asubstrate; forming a plurality of recess patterns by etching regions inwhich floating gates are to be formed in the active region between thedevice isolation layers to a predetermined depth; forming a tunnel oxidelayer over the recess patterns; forming a plurality of recessed floatinggates buried into the recess patterns over the tunnel oxide layer; andforming a plurality of stack structures by stacking a plurality ofdielectric layers and a plurality of control gates in a directionperpendicular to the device isolation layers to cover upper portions ofthe recessed floating gates.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects and features of the present invention willbecome better understood with respect to the following description ofthe preferred embodiments given in conjunction with the accompanyingdrawings, in which:

FIG. 1 is a top view illustrating a typical flash memory device;

FIGS. 2A and 2B are cross-sectional views illustrating FIG. 1 cut alonga line I-I′ and a line II-II′ respectively;

FIG. 3 is a top view illustrating a flash memory device in accordancewith a specific embodiment of the present invention;

FIGS. 4A and 4B are cross-sectional views illustrating FIG. 3 cut alonga line I-I′ and a line II-II′ respectively; and

FIGS. 5A to 5H are cross-sectional views illustrating a method forfabricating a flash memory device in accordance with a specificembodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, detailed descriptions of certain embodiments of the presentinvention will be provided with reference to the accompanying drawings.

FIG. 3 is a top view illustrating a flash memory device in accordancewith a specific embodiment of the present invention. FIGS. 4A and 4B arecross-sectional views illustrating FIG. 3 cut along a line I-I′ and aline II-II′ respectively.

As shown in FIG. 3, a plurality of device isolation layers 27 are formedin a substrate 21 spaced apart a predetermined distance in the samedirection. A plurality of recessed floating gates RFG 31A are formed inrecess patterns provided in an active region 21A between the deviceisolation layers 27. A plurality of control gates CG 26 covering therecessed floating gates RFG 31A are placed in a direction perpendicularto the device isolation layers 27.

Referring to FIGS. 4A and 4B to examine the recessed floating gates RFG31A, a plurality of device isolation layers 27 with trench structuresare formed in a substrate 21 spaced apart a predetermined distance. Atthis time, an active region 21A is formed between the device isolationlayers 27, and each of the device isolation layers 27 is formed with aheight higher than a surface of the active region 21A.

The active region 21A has a plurality of recess patterns 29B. Aplurality of stack structures, each formed by stacking a tunnel oxidelayer 30 and a recessed floating gate RFG 31A, are formed inside therecess patterns 29B. Herein, a surface of the recessed floating gatesRFG 31A is identical to a surface of the device isolation layers 27insulating a portion between recessed floating gates RFG 31A. Therecessed floating gates RFG 31A are formed with polysilicon. The recesspatterns 29B are insulated from each other by the device isolationlayers 27 in a longitudinal direction to a control gate CG, and areisolated from each other by the active region 21A in a longitudinaldirection to the active region 21A.

An oxide/nitride/oxide (ONO) layer 32, a second polysilicon layer 33, atungsten silicide layer 34, a silicon oxynitride layer 35 and a hardmask oxide layer 36 are sequentially stacked over each of the recessedfloating gates RFG 31A. Herein, each of control gates CG is formedstacking the second polysilicon layer 33 and the tungsten silicide layer34.

As shown in FIGS. 3, 4A and 4B, floating gates FG are formed in therecessed floating gates RFG 31A buried into the recess patterns 29B.Thus, an effective gate length defined by each of the recessed floatinggates 31A becomes CH2. Herein, CH2 is longer than an effective gatelength of the conventional planar type structure by a depth of theindividual recess pattern 29B, i.e., practically twice as long as thedepth of the individual recess pattern 29B. That is, it is possible toincrease an effective gate length without increasing a dopingconcentration of the substrate.

FIGS. 5A to 5H are cross-sectional views illustrating a method forfabricating a memory device in accordance with a specific embodiment ofthe present invention. Among FIGS. 5A to 5H, the figures placed in theleft side are cross-sectional views illustrating FIG. 3 cut along theline I-I′ and the figures placed in the right side are cross-sectionalviews illustrating FIG. 3 cut along the line II-II′.

As shown in FIG. 5A, a patterned threshold voltage (Vt) screen oxidelayer 22, a patterned ISO nitride layer 23, a patterned ISO oxide layer24, and a patterned ISO hard mask 25 are sequentially stacked over apatterned substrate 21.

Although not shown, the process of forming the patterned thresholdvoltage (Vt) screen oxide layer 22, the patterned ISO nitride layer 23,the patterned ISO oxide layer 24, and the patterned ISO hard mask 25,and the patterned substrate 21 are explained hereinafter.

A Vt screen oxide layer, an ISO nitride layer, an ISO oxide layer, andan ISO hard mask are sequentially deposited over a substrate to performa shallow trench isolation (STI) process. Herein, the substrate isdefined with a cell array region and a peripheral region.

The Vt screen oxide layer is deposited to function as a thermal oxidelayer in a thickness ranging from approximately 50 Å to approximately100 Å in a diffusion furnace at a temperature of approximately 900° C.and an oxide atmosphere.

The ISO nitride layer is deposited with a thickness of approximately 500Å at a temperature of approximately 760° C. with supply of a pressure ofapproximately 0.35 torr by flowing approximately 50 cc of nitrogen (N₂),approximately 90 cc of dichlorosilane (SiH₂Cl₂), and approximately 90 ccof ammonia (NH₃).

Both the ISO oxide layer and the ISO hard mask are formed in a thicknessof approximately 300 Å. The ISO hard mask is formed by using siliconoxynitride (SiON).

Next, the ISO hard mask is patterned by using an ISO mask (not shown)and afterwards, the ISO mask is stripped. Herein, the patterned ISO hardmask is denoted with a reference numeral 25. The ISO oxide layer, theISO nitride layer, and the Vt screen oxide layer are sequentially etchedby using the patterned ISO hard mask 25 as an etch mask. Herein, thepatterned ISO oxide layer, the patterned ISO nitride layer, and thepatterned Vt screen oxide layer are denoted with reference numerals 24,23, and 22 respectively.

Next, the substrate exposed after etching the Vt screen oxide layer isetched to a predetermined depth. Herein, the patterned substrate isdenoted as a reference numeral 21. Then, a plurality of trenches 26 fordevice isolation are formed and a portion except for the trenches 26 isdefined as an active region 21A. At this time, the trenches 26 areformed with a depth of approximately 2,000 Å. The etching process of theISO hard mask to the substrate is carried out in-situ by using a dryetching process. Etchant used in the etching process for forming thetrenches 26 comprises a fluorine-based gas selected from the groupconsisting of tetrafluoromethane (CF₄), hexafluoroethane (C₂F₆),octafluorocyclobutane (C₄F₈), hexafluorobutadiene (C₄F₆),octafluorocyclopentene (C₅F₈), trifluoromethane (CF₃H), Carbon fluoridehydride (CF₂H₂), methy fluoride (CFH₃), pentafluoroethane (C₂HF₅),nitrogen trifluoride (NF₃), sulphur hexafluoride (SF₆) and CF₃Cl. A gasadditive to the etchant is one of hydrogen (H₂) and oxygen (O₂).

As shown in FIG. 5B, a gap-fill layer 27 is deposited until trenches 26are filled. The gap-fill layer 27 is formed with a high density plasmaoxide layer. At this time, a deposition thickness of the gap-fillinsulation layer 27 should be optimized to isolate the cell region andthe peripheral region without generating a dishing phenomenon or erosionduring a subsequent chemical mechanical polishing (CMP) process. Forinstance, the gap-fill layer 27 is deposited with a thickness rangingfrom approximately 5,000 Å to approximately 8,000 Å. Meanwhile, afterthe gap-fill insulation layer 27 made of the high density plasma oxidelayer is deposited, an annealing is performed at a temperature of 1,050°C. in a nitrogen atmosphere for approximately 30 minutes and thus,quality of the layer becomes dense.

A first CMP process is performed by using silica slurry to remove a highheight difference over the active region 21A. A second CMP process isperformed by using ceria slurry. Thus, uniformity of the gap-fillinsulation layer 27 is improved in the cell array region and theperipheral region, and the gap-fill insulation layer 27 is isolated fromeach other.

During the CMP process, the ceria slurry has a high polishingselectivity of the gap-fill insulation layer 27 formed with the highdensity plasma oxide layer to the patterned ISO nitride layer 23 formedwith the silicon nitride layer. However, a height removing capability ofthe ceria slurry is lower than the silica slurry. Thus, a predeterminedportion of the gap-fill insulation layer 27 is planarized in advancebefore using the ceria slurry to remove the height difference. Then, thegap-fill insulation layer 27 is isolated from each other by using theceria slurry having high selectivity slurry (HSS).

During the CMP process performed twice, the patterned ISO layer 23serves a role of a polishing stop layer. Accordingly, during the CMPprocess, the gap-fill insulation layer 27, the patterned ISO hard mask25 and the patterned ISO oxide layer 24 are polished.

Hereinafter, the isolated gap-fill insulation layer 27 is referred to asdevice isolation layers 27. A surface of each of the device isolationlayers 27 is higher than that of the active region 21A.

As shown in FIG. 5C, the patterned ISO layer 23 and the patterned Vtoxide layer 22 remaining after planarizing the device isolation layers27 are stripped.

Herein, before stripping the patterned ISO nitride layer 23, thepatterned ISO nitride layer 23 is dipped into a solution of bufferedoxide etchant (BOE) to remove the device isolation layers 27 which mayremain over the patterned ISO nitride layer 23 and then, stripped byusing phosphoric acid (H₃PO₄) solution. Afterwards, the patterned Vtscreen oxide layer 22 is stripped by using a solution of hydrogenfluoride (HF). At this time, a stripping time can be controlled not togenerate a moat around a boundary region between a top corner of theactive region 21A and the device isolation layers 27.

After the stripping process, the device isolation layers 27 are formedin a type insulting portions of the active region 21A, and the deviceisolation layers 27 are formed higher than the active region 21A.

As shown in FIG. 5D, a photoresist layer is formed over an entiresurface of the resulting structure including the device isolation layers27. The photoresist layer is patterned by performing a photo-exposureprocess and a developing process, thereby forming a recess mask 28. Atthis time, the recess mask 28 can be formed as a reverse mask of acontrol gate mask used to pattern a subsequent control gate. That is,the reverse mask exposes a gate material to be covered by the controlgate mask and covers a portion to be etched. Typically, a portioncovered by the control gate mask becomes a control gate after theetching process.

Accordingly, the recess mask 28 has an opening which opens an upperportion of the active region 21A and the device isolation layers 27placed in a direction perpendicular to the control gate. For instance,the opening of the recess mask 28 is placed in a direction perpendicularto the device isolation layers 27 placed in the same direction to theopening of the recess mask 28.

As show in FIG. 5E, a plurality of recess patterns 29B are formed byetching predetermined portions of the active region 21A. At this time,the active region 21A is recessed to a predetermined depth by using therecess mask 28 formed in a direction perpendicular to the deviceisolation layers 27.

Accordingly, the active region 21A is classified into a plurality ofsurface regions 29A and the plurality of recess patterns 29B lower thanthe recess regions 21A. In more detail, predetermined portions of theactive region 21A are recessed to have a predetermined distance, therebyforming the recess patterns 29B and the surface regions 29A between therecess patterns 29B. The recess patterns 29B are insulated by the deviceisolation layers 27 at a direction which a control gate is formed. Also,the recess patterns 29B have isolated structures since the recesspatterns 29B are isolated from each other by each of the surface regions29A at a direction of the active region 21A.

The most important factor in the etching process for forming the recesspatterns 29B is an etch profile. A depth of the individual recesspattern 29B should be uniform and a horn should not be generated ininner edges of the profile of the individual recess pattern 29B.

For instance, etchant used in the etching process for forming the recesspatterns 29B comprises a gas selected from the group consisting of CF₄gas, C₂F₆ gas, C₄F₈ gas, C₄F₆ gas, C₅F₈ gas, CF₃H gas, CF₂H₂ gas, CFH₃gas, C₂HF₅ gas, NF₃ gas, SF₆ gas, and CF₃Cl gas. Also, a gas additive tothe etchant uses H₂ gas or O₂ gas. An etch target, i.e., a depth to beetched, ranges from approximately 800 Å to approximately 1,500 Å. If theetching process is performed with the above described condition, thehorn is not generated.

As shown in FIG. 5F, the recess mask 28 is stripped.

A tunnel oxide layer 30 is formed over the surface regions 29A and therecess patterns 29B and then, a first polysilicon layer 31 is formedover the tunnel oxide layer 30. At this time, the tunnel oxide layer isformed with a thickness ranging from approximately 50 Å to approximately100 Å. A thickness of the first polysilicon layer 31 ranges fromapproximately 1,000 Å to approximately 2,000 Å in consideration of adepth to be removed during a subsequent CMP process.

As shown in FIG. 5G, the first polysilicon layer 31 is planarized byperforming a polysilicon CMP process to form plurality of floating gates31A made of the first polysilicon. At this time, the floating gates 31Aare isolated from each other by the device isolation layers 27.

Slurry used in the polysilicon CMP process has a very high selectivityof polysilicon to the tunnel oxide layer 30. The tunnel oxide layer 30serves a role of a CMP barrier and thus, the patterned substrate 21 isnot attacked and a dishing phenomenon, i.e., a dishing phenomenon with athickness of approximately 50 Å, is minimized in upper portions of thefloating gates 31A.

The aforementioned slurry has a very high etch selectivity ofapproximately 200 parts of polysilicon, i.e., approximately 200 parts toapproximately 300 parts of polysilicon, to approximately 1 part of thetunnel oxide layer. This slurry having very high etch selectivity ratiohas an etch selectivity of approximately 200 parts of polysilicon toapproximately 1 part of the high density plasma oxide layer used as thedevice isolation layers 27.

As described above, the floating gates 31A are buried into the recesspatterns 29B. Accordingly, hereinafter, the floating gates 31A arereferred to as recessed floating gates 31A.

As shown in FIG. 5H, a patterned hard mask oxide layer 36, a patternedsilicon oxynitride layer 35, a patterned tungsten silicide layer 34, apatterned second polysilicon layer 33 and a patternedoxide/nitride/oxide (ONO) layer 32 are formed over the recessed floatinggates 31A. Although not shown, a process of forming the patterned hardmask oxide layer 36, the patterned silicon oxynitride layer 35, thepatterned tungsten silicide layer 34, the patterned second polysiliconlayer 33 and the patterned ONO layer 32 is explained hereinafter. An ONOlayer, a second polysilicon layer, a tungsten silicide layer, a siliconoxynitride layer, and a hard mask oxide layer are sequentially formedover an entire surface of the resulting structure including the recessedfloating gates 31A. Herein, when forming the ONO layer, oxygen (O) isdeposited with a thickness ranging from approximately 30 Å toapproximately 50 Å; nitrogen (N) is deposited with a thickness rangingfrom approximately 30 Å to approximately 50 Å; and oxygen (O) isdeposited with a thickness ranging from approximately 50 Å toapproximately 70 Å. The second polysilicon layer is deposited with athickness of approximately 2,000 Å, and the tungsten silicide layer isdeposited with a thickness ranging from approximately 1,000 Å toapproximately 1,500 Å. The silicon oxynitride layer is deposited with athickness ranging from approximately 200 Å to approximately 300 Å, andthe hard mask oxide layer is deposited with a thickness ranging fromapproximately 1,500 Å to approximately 2,000 Å.

Next, the hard mask layer, the silicon oxynitride layer, the tungstensilicide layer, the second polysilicon layer, and the ONO layer areetched by performing an etching process using a control gate mask (notshown). Herein, the patterned hard mask layer, the patterned siliconoxynitride layer, the patterned tungsten silicide layer, the patternedsecond polysilicon layer, and the patterned ONO layer are denoted withreference numerals 36, 35, 34, 33, and 32 respectively. A plurality ofcontrol gates CG are formed by stacking the patterned second polysiliconlayer 33 and the patterned tungsten silicide layer 34.

In accordance with the present invention, during forming a flash memorydevice, the floating gates are formed as the recess floating gates 31Aburied into the recess patterns 29B and thus, an effective gate lengthdefined by each of the recess floating gates 31A becomes CH2. Herein,CH42 is longer than an effective gate length of a planar type gatestructure by a depth of the individual recess pattern 29B, i.e., twicethe depth of the individual recess pattern 29B.

In accordance with the present invention, it is possible to increase aneffective gate length if a flash memory device with a size ofapproximately sub 60 nm is fabricated using recess patterns, i.e.,recess channels. Accordingly, an electrical property of the device canbe improved without increasing a doping concentration of a substrate.

The present application contains subject matter related to the Koreanpatent application No. KR 2005-0115670, filed in the Korean PatentOffice on Nov. 30, 2005, the entire contents of which being incorporatedherein by reference.

While the present invention has been described with respect to certainpreferred embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the spirit and scope of the invention as defined in the followingclaims.

1. A method for fabricating a flash memory device, comprising: forming aplurality of device isolation layers with a trench structure and aheight greater than that of a surface of an active region in asubstrate; forming a plurality of recess patterns by etching regions inwhich floating gates are to be formed in the active region between thedevice isolation layers to a predetermined depth; forming a tunnel oxidelayer over the recess patterns; forming a plurality of recessed floatinggates buried into the recess patterns over the tunnel oxide layer; andforming a plurality of stack structures by stacking a plurality ofdielectric layers and a plurality of control gates in a directionperpendicular to the device isolation layers to cover upper portions ofthe recessed floating gates.
 2. The method of claim 1, wherein theforming of the plurality of recess patterns includes: forming aphotoresist layer over the device isolation layers; performing aphoto-exposure process and a developing process to the photoresist layerto form a line type recess mask opening the portions in which thefloating gates are to be formed; etching the opened portions in whichthe floating gates are to be formed by using the recess mask as an etchmask, thereby forming the recess patterns; and stripping the recessmask.
 3. The method of claim 2, wherein the etching of the openedportions includes using a fluorine-based gas as etchant.
 4. The methodof claim 3, wherein the fluorine-base gas includes one selected from thegroup consisting of CF₄ gas, C₂F₆ gas, C₄F₈ gas, C₄F₆ gas, C₅F₈ gas,CF₃H gas, CF₂H₂ gas, CFH₃ gas, C₂HF₅ gas, NF₃ gas, SF₆ gas, and CF₃C1gas.
 5. The method of claim 4, wherein one of H₂ gas and O₂ gas is addedto the fluorine-based gas.
 6. The method of claim 2, wherein the etchingof the opened portions includes an etch target ranging fromapproximately 800 Å to approximately 1,500 Å.
 7. The method of claim 1,wherein the forming of the plurality of recessed floating gatesincludes: forming a conductive layer over the tunnel oxide layer untilthe recess patterns are filled; and planarizing the conductive layeruntil the tunnel oxide layer existing over portions except the recesspatterns is exposed, thereby forming the recessed floating gates insidethe recess patterns.
 8. The method of claim 7, wherein the forming ofthe conductive layer includes depositing silicon with a thicknessranging from approximately 1,000 Å to approximately 2,000 Å.
 9. Themethod of claim 8, wherein the planarizing of the conductive layerincludes performing a polysilicon chemical mechanical polishing (CMP)process.
 10. The method of claim 9, wherein the polysilicon CMP processuses slurry having a high etch selectivity of polysilicon to an oxidelayer.
 11. The method of claim 10, wherein the slurry has an etchselectivity of approximately 200 to approximately 300 parts ofpolysilicon to approximately 1 part of a tunnel oxide layer.
 12. Themethod of claim 1, wherein the forming of the plurality of deviceisolation layers includes: forming a trench mask over the substrate;etching the substrate to a predetermined thickness by using the trenchmask as an etch mask, thereby forming a plurality of trenches definingthe active region; forming a gap-fill insulation layer for deviceisolation in the trenches; planarizing the gap-fill insulation layeruntil a surface of the trench mask is exposed; and removing the trenchmask.
 13. The method of claim 12, wherein the planarizing of thegap-fill insulation layer includes sequentially employing a first CMPprocess using silica slurry and a second CMP process using ceria slurry.14. The method of claim 13, wherein the forming of the trench maskincludes sequentially stacking an oxide layer and a nitride layer. 15.The method of claim 14, wherein the removing of the trench maskincludes: removing the gap-fill insulation layer remaining over an upperportion of the trench mask after planarizing the gap-filled insulationlayer; stripping the nitride layer of the trench mask; and stripping theoxide layer of the trench mask.
 16. The method of claim 15, wherein theremaining gap-filled insulation layer is dipped into a buffered oxideetchant (BOE) to be removed; the nitride layer is stripped by using asolution of phosphoric acid (H₃PO₄); and the oxide layer is stripped byusing a solution of hydrogen fluoride (HF).
 17. The method of claim 1,wherein the forming of the plurality of stack structures includes:forming the dielectric layers over the recessed floating gates; forminga conductive layer for the control gates over the dielectric layers;forming a silicon oxynitride layer over the conductive layer for thecontrol gates; forming a hard mask oxide layer over the siliconoxynitride layer; forming a control gate mask over the hard mask oxidelayer; etching the hard mask oxide layer, the silicon oxynitride layer,the conductive layer for the control gates and the dielectric layer byusing the control gate mask as an etch mask; and removing the controlgate mask.
 18. The method of claim 17, wherein the forming of theconductive layer for the control gates includes stacking polysilicon andtungsten silicide.